1. Technical Field
The present invention relates to a test apparatus, a program, and a test method. More particularly, the present invention relates to a test apparatus, a program, and a test method for controlling an address value of an address to be supplied to a memory under test.
2. Related Art
In the present memory device, a memory input address that is input to designate a storage cell from the outside and a physical address that shows arrangement of storage cells within the memory device are different from each other. That is to say, the memory device translates a memory input address designated from the outside into a physical address according to a data reading request, and then outputs the contents of a storage cell designated by the physical address. By doing in this way, although a continuous memory area is designated from the outside, it is possible to improve an access speed by alternately accessing a plurality of memory banks and access a preliminary storage cell in place of a storage cell proved to be false after manufacturing.
Now, since a related patent document is not recognized, the description is omitted.
A physical position of each storage cell may relate to badness for the memory device. For example, when a memory device has wiring badness, data written in a certain storage cell may be written in another storage cell adjacent to the storage cell. In order to detect such badness, it is necessary that a test apparatus writes data in a certain storage cell and reads data from another storage cell adjacent to the storage cell. For this reason, it is desirable that the test apparatus can access each storage cell by means of a physical address.
In order to realize this, a conventional test apparatus has a translation memory that stores a translation table for translating a physical address into a memory input address. This translation memory stores a memory input address in an address designated by a physical address. A conventional test apparatus translates a generated physical address into a memory input address by means of this translation memory and supplies the translated address to a device under test. However, when bus width of an address of a memory device increases with high performance of the memory device, necessary capacitance of the translation memory increases and thus maintenance and management costs for the test apparatus may increase.